1. Field of the Invention
This disclosure relates to a split-gate nonvolatile semiconductor memory device and a method of manufacturing the same. More particularly, the disclosure relates to a split-gate nonvolatile semiconductor memory device, in which a control gate is formed in a self-aligned manner, and a method of manufacturing the same.
2. Description of the Related Art
As a nonvolatile memory device can electrically erase and store data and retain data even if power supply is interrupted, the nonvolatile memory device has increasingly been applied in various fields such as mobile communication systems and memory cards. The nonvolatile semiconductor memory device includes a transistor, which can be categorized as a stack-gate transistor or a split-gate transistor. The stack-gate transistor includes a floating gate, an insulating layer, and a control gate, which are sequentially stacked, and the split-gate transistor includes a split-gate structure.
FIG. 1 is a cross-sectional diagram illustrating a conventional nonvolatile semiconductor memory device with a split-gate transistor (hereinafter, referred to as a “split-gate memory device”).
Referring to FIG. 1, in the conventional split-gate memory device, a source region 15 is formed in a predetermined region of a semiconductor substrate 10, and a pair of floating gates 20 is disposed adjacent to each other on the semiconductor substrate 10 on both sides of the source region 15. A top surface of each of the floating gates 20 is covered by an elliptical oxide layer 25. A sidewall of each of the floating gates 20 on the opposite side of the source region 15 is covered by a control gate 30. The control gate 30 extends from the sidewall of the floating gate 20, covers a top surface of the elliptical oxide layer 25 in one direction, and covers a portion of the semiconductor substrate 10 outside the floating gate 20 on the opposite side of the source region 15 in another direction. A drain region 35 is formed in the semiconductor substrate 10 adjacent to the control gate 30. A portion of the control gate 30 overlaps the drain region 35. A gate insulating layer 40 is formed between the floating gate 20 and the semiconductor substrate 10. The gate insulating layer 40, which is under a bottom of the floating gate 20, is also under a tunnel insulating layer 45. A portion of the tunnel insulating layer 45 extends from the sidewall of the floating gate 20 and is located between the control gate 30 and the semiconductor substrate 10. The tunnel insulating layer 45 is patterned to conform to the shape of the control gate 30.
As described above, the split-gate memory device includes the floating gate 20 and the control gate 30, which are separated from each other. The floating gate 20 has an electrically isolated structure. Electrons are injected into the floating gate 20 to write data, and the electrons are emitted from the floating gate 20 to erase data. Data is stored in a memory cell using a change of a cell current that is caused by the injection or emission of electrons. In a write mode, if a high voltage (e.g., 15 V or higher) is applied to the source region 15 and an appropriate voltage is applied to the drain region 35, hot electrons are injected from the semiconductor substrate 10, which is positioned below the floating gate 20 adjacent to the control gate 30, via the gate insulating layer 40 into the floating gate 20. In an erase mode, if a voltage of 15 V or higher is applied to the control gate 30, a high electric field is applied to tips of the floating gate 20 such that the electrons are emitted from the floating gate 20 and injected into the control gate 30. Hence, the injection of electrons into the floating gate 20 is performed using channel hot electron injection (CHEI), while the emission of electrons from the floating gate 20 is performed by Fowler-Nordheim tunneling through the tunnel insulating layer 45 between the floating gate 20 and the control gate 30.
The foregoing split-gate memory device can be manufactured by, for example, the following method. Initially, a gate insulating layer 40 is formed on an entire surface of a semiconductor substrate 10. A first polysilicon layer is formed to a predetermined thickness on the gate insulating layer 40 and then patterned using a photolithography process. Next, the first polysilicon layer is thermally oxidized. Then, the floating gate 20 and an elliptical oxide layer 25, which covers a top surface of the floating gate 20, are formed.
Thereafter, an insulating layer is formed on the entire surface of the semiconductor substrate 10 where the elliptical oxide layer 25 is formed, using chemical vapor deposition (CVD) or the like. The insulating layer is patterned using a photolithography process to thereby form a tunnel insulating layer 45 as shown in FIG. 1.
Thereafter, a process of forming a control gate 30 is performed. For example, to form a polysilicon control gate 30, a second polysilicon layer is formed by depositing polysilicon conformally on the resultant structure where the tunnel insulating layer 45 is formed and patterned.
As described above, in the conventional method, a photolithography process is used to pattern the control gate 30 and the floating gate 20 and define the lengths and sizes thereof. However, a misalignment and a loading effect may occur during the photolithography process, and the misalignment may cause a large variation in the overlap length.
A misalignment causes a difference in the effective channel length of the control gate 30 between cells. Thus, two cells, i.e., an even cell and an odd cell, which are disposed symmetrically in mirror-image relations as shown in FIG. 1, have different characteristics since the effective channel length of the even cell L1 differs from the effective channel length of the odd cell L2. This variation in the effective channel length of the control gate 30 leads to a variation in the threshold voltage of memory cells. Also, since the size of the floating gate 20 is defined by the photolithography process, it is very difficult to scale down the floating gate 20 below the exposure limit of a photolithography apparatus.
Embodiments of the invention address these and other disadvantages of the conventional art.